CMOS image sensors are increasingly being used as low cost imaging devices. A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells includes a photo-conversion device, such as a pinned photodiode, having an associated a charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a sensing node, which is typically a floating diffusion region, and a transistor, for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The pixel cell may also include a source follower transistor for receiving and amplifying charge from the sensing node and an access transistor for controlling the readout of the cell contents from the source follower transistor.
CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,”IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,”IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524, assigned to Micron Technology, Inc., which describe operation of conventional CMOS image sensors, the contents of which are incorporated herein by reference.
A schematic diagram of a conventional CMOS pixel cell 10 is shown in FIG. 1. The CMOS pixel cell 10 comprises a pinned photodiode 21 for collecting charges generated by light incident on the pixel, and a transfer transistor 50 for transferring photoelectric charges from the pinned photodiode 21 to a floating diffusion region 25. The floating diffusion region 25 is electrically connected to the gate of an output source follower transistor 60. The pixel cell 10 also includes a reset transistor 40 for resetting the floating diffusion region 25 to a predetermined voltage before sensing a signal, and a row select transistor 80 for outputting a signal from the source follower transistor 60 to an output terminal in response to an address signal.
FIG. 2 is a timing diagram illustrating the operation of the pixel cell 10. In the pixel cell 10, charge is generated by the pinned photodiode 21 in response to light incident on the cell 10 and accumulated by the pinned photodiode 21 during an integration period. During a readout procedure, the photo-generated charge is transferred to readout circuitry and readout as follows.
For readout, a row select signal (ROW) is pulsed high to activate the gate of the row select transistor 80. At approximately the same time, a reset signal (RST) is pulsed high to activate the gate of the reset transistor 40 and to reset the floating diffusion region 25 to a predetermined voltage Vpix. To obtain a reset signal Vrst, the voltage on the floating diffusion region 25 is applied to the gate of the source follower transistor 60 and readout through the row select transistor 80 to a sample and hold circuit (not shown). For this operation, as RST goes low, a sample and hold reset signal (SHR) is pulsed high and then low to cause the sample and hold circuit to sample and store the reset signal Vrst.
Subsequently, the photo-generated charge is readout to obtain a pixel signal Vphoto. For this, a transfer signal (TX) is pulsed high to operate a gate of the transfer transistor 50 and to transfer the photo-generated charge from the pinned photodiode 21 to the floating diffusion region 25. The voltage on the floating diffusion region 25 is applied to the gate of the source follower transistor 60 and readout through the row select transistor 80 to the sample and hold circuit. As TX goes low, a sample and hold signal pixel signal (SHS) is pulsed high and then low to cause the sample and hold circuit to sample and store the pixel signal Vphoto. After the readout process is complete, ROW goes low to deactivate the gate of the row select transistor 80.
A potential barrier may exist between the pinned photodiode 21 and the floating diffusion region 25. FIG. 3 is a potential well diagram of the pinned photodiode 21 and the floating diffusion region 25 and shows a potential barrier 30 between the pinned photodiode 21 and the floating diffusion region 25. This barrier 30 causes incomplete charge transfer and makes the pinned photodiode potential behind the barrier difficult to control. Additionally, this potential barrier 30 leads to image lag.
Image lag includes two components: charging lag and discharging lag. Charging lag is most apparent when a pixel cell has been functioning for a time under dark conditions. FIGS. 4A-4D are potential well diagrams of the pinned photodiode 21 and the floating diffusion region 25 illustrating charging lag. Initially, as shown in FIG. 4A, the potential well of the pinned photodiode 21 is filled with charge (i.e. electrons) to a point below the barrier 30 and the potential of the pinned photodiode 21 is approximately equal to the barrier potential.
During operation in dark conditions, when the transfer gate periodically opens, the potential well of the pinned photodiode 21 becomes partially depleted, as shown in FIG. 4B, and the potential of the pinned photodiode 21 increases. As shown in FIG. 4C, when the pixel cell 10 subsequently integrates light, a portion of the charge 31 generated from that light serves to replenish the depleted potential of the photodiode 21. Accordingly, as shown in FIG. 4D, when the photo-generated charge is transferred to the floating diffusion region 25, the portion of photo-generated charge 31 is prevented from being transferred by the barrier 30 and the charge 31 remains in the pinned photodiode 21 so that the potential of pinned photodiode 21 is again equal to the potential barrier 30.
Consequently, the portion of photo-generated charge 31 is lost and is not readout as part of a pixel image signal. The longer the pixel cell 10 operates under dark conditions, the more depleted the potential well of the photodiode 21 becomes and, therefore, the greater the loss of charge from a first integration period. Charging lag causes non-linearity of signal response, referred to as a “dead” zone with low responsivity at small exposures, and smearing of moving objects.
Discharging lag is associated with a signal from a prior frame appearing as a ghost image in subsequent frames. Discharging lag is likely caused by the potential barrier's 30 dependence on the potential of the floating diffusion region 25 and/or by incomplete charge transfer from the pinned photodiode 21 to the floating diffusion region 25 during a readout cycle. FIGS. 5A through 5D are potential well diagrams of the pinned photodiode 21 and floating diffusion region 25, which illustrate discharging lag
As shown in FIG. 5A, initially, the potential barrier 30 has a height H1, when the floating diffusion region 25 has been reset to a predetermined potential, and is free from any photo-generated charge. Also, the potential well of the pinned photodiode 21 is filled with charge to a point below the barrier 30 and the potential of the pinned photodiode 21 is approximately equal to the barrier potential 30. FIG. 5B illustrates the accumulation of photo-generated charge 33 by the photodiode 21.
As the photo-generated charge 33 is transferred to the floating diffusion region 25, the potential on the floating diffusion region 25 decreases and the height of the barrier 30 increases to H2, as shown in FIG. 5C. Consequently, a first portion of photo-generated charge 34 remains in the potential well of pinned photodiode 21, as a second portion of photo-generated charge 35 is transferred to the floating diffusion region 25. As shown in FIG. 5D, when the second portion of photo-generated charge 35 is readout from the floating diffusion region 25, the potential of the floating diffusion region 25 increases and the height of the barrier 30 decreases to H3, which is approximately equal to H1, and the first portion of photo-generated charge 34 is transferred to the floating diffusion region 25. The first portion of photo-generated charge 34 is then readout with subsequently integrated charge, causing a ghost image in the subsequent frame.
Often, techniques to reduce lag result in an undesirable increase in reset noise in a pixel cell. Some techniques, however, have been suggested that provide improved lag characteristics without increasing reset noise. See B. Pain et al., “Analysis and Enhancement of Low-light-level Performance of Photodiode-type CMOS Active Pixel Images Operated With Sub-threshold Reset,”in 1999 IEEE Workshop on CCDs and AIS, (Nagano, Japan), June 1999; H. Tian et al. “Analysis of Temporal Noise CMOS Photodiode Active Pixel Sensor,” IEEEJ. of Solid-State Circuits, Vol. 36, No. 1, pp. 92-101, (2001), which are incorporated herein by reference. Although these techniques improve lag and reduce reset noise, further noise reduction and alternative methods for reducing lag are needed for CMOS image sensors.
Accordingly, there is a need for a CMOS pixel cell and a method of operating the pixel cell to achieve lag cancellation and reduced reset noise.